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Analog-to-digital converter (ADC)
Figure 39. Alternate + Regular simultaneous
1st trig
RM0008
ADC1 reg
CH0
CH1
CH2
CH2
CH3
CH3
CH4
ADC1 inj
CH0
ADC2 reg
CH3
CH5
CH6
CH6
CH7
CH7
CH8
ADC2 inj
CH0
synchro not lost
2nd trig
If a trigger occurs during an injected conversion that has interrupted a regular conversion, it
will be ignored. Figure 40 shows the behavior in this case (2nd trig is ignored).
Figure 40. Case of trigger occurring during injected conversion
1st trig
3rd trig
ADC1 reg
CH0
CH1
CH2
CH2
CH3
CH3
CH4
ADC1 inj
CH0
CH0
ADC2 reg
CH3
CH5
CH6
CH6
CH7
CH7
CH8
ADC2 inj
2nd trig
CH0
4th trig
11.9.9
Note:
Combined injected simultaneous + interleaved
It is possible to interrupt an interleaved conversion with an injected event. In this case the
interleaved conversion is interrupted and the injected conversion starts, at the end of the
injected sequence the interleaved conversion is resumed. Figure 41 shows the behavior
using an example.
When the ADC clock prescaler is set to 4, the interleaved mode does not recover with
evenly spaced sampling periods: the sampling interval is 8 ADC clock periods followed by 6
ADC clock periods, instead of 7 clock periods followed by 7 clock periods.
Figure 41. Interleaved single channel with injected sequence CH11, CH12
Sampling
ADC1
ADC2
CH0
CH0
CH0
CH0
CH0
CH0
Conversion
CH11
CH12
Trigger
CH12
CH11
CH0
CH0
CH0
CH0
216/995
Doc ID 13902 Rev 9
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